library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div_frequency is
port(clk:in std_logic;
		rise: out std_logic);
end entity div_frequency;

architecture funs of div_frequency is
begin
	upcount:process(clk) is
	variable count:integer:=0;
	begin 
	if(clk'event and clk='1')then    
		if count=49999999 then
			rise<='1';
			count:=0;
		else rise<='0';count:=count+1;
		end if;	  		
	end if; 
end process upcount; 

end architecture funs; 